 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| SL1062A Low Voltage Transmission Circuit with Dialler Interface The SL1062A is an integrated circuit that perform all speech and line interface functions required in fully electronic telephone sets. They perform electronic switching between dialling and speech. The ICs operate at line voltage down to 1.6 V DC (with reduced performance) to facilitate the use of more telephone sets connected in parallel. * Low DC line voltage: operates down to 1.6 V (excluding polarity guard) * Voltage regulator with adjustable static resistance * Provides a supply for external circuits * Symmertical high-impedance inputs (64 K) for dynamic, magnetic or piezo-electric microphones * Asymmetrical high-impedance input (32 K) for electret microphones * DTMF signal input with confidence tone * Mute input for pulse or DTMF dialing: active LOW (MUTE) * Receiving amplifier for dynamic, magnetic or piezo-electric earpieces * Large gain setting ranges on microphone and earpiece amplifiers * Line loss compensation (line current dependent) for microphone and earpiece amplifiers * Gain control curve adaptable to exchange supply * DC line voltage adjustment facility ORDERING INFORMATION SL1062AN Plastic TA = -25 to 75 C for package PIN ASSIGNMENT BLOCK DIAGRAM SLS System Logic Semiconductor SL1062A PIN DESCRIPTION Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Designation LN GAS1 GAS2 QR GAR MICMIC+ STAB VEE IR DTMF MUTE VCC REG AGC SLPE Description positive line terminal gain adjustment; transmitting amplifier gain adjustment; transmitting amplifier non-inverting output; receiving amplifier gain adjustment; receiving amplifier inverting microphone input non-inverting microphone input current stabilizer negative line terminal receiving amplifier input dual-tone multi-frequency input mute input possitive supply decoupling voltage regulator decoupling automatic gain control input slope (DC resistance) adjustment FUNCTIONAL DESCRIPTION Supplies VCC, LN, SLPE, REG and STAB Power for the IC and its peripheral circuits is usually obtained from the telephone line. The supply voltage is derived from the line via a dropping resistor and regulated by the IC. The supply voltage VCC may also be used to supply external circuits e.g. dialling and control circuits. Decoupling of the supply voltage is performed by a capacitor between VCC and VEE. The internal voltage regulator is decoupled by a capacitor between REG and VEE. The DC current flowing into the set is determined by the exchange supply voltage Vexch, the feeding bridge resistance Rexch and the DC resistance of the telephone line Rline. The circuit has an internal current stabilizer operating at a level determined by a 3.6 K resistor connected between STAB and VEE (see Fig.1). Figure 1. Supply arrengement When the line current (Iline) is more than 0.5 mA greater than the sum of the IC supply current (ICC) and the current draw by the peripheral circuitry connected to VCC (Ip) the excess current is shunted to VEE via LN. The regulated voltage on the line terminal (VLN) can be calculated as: VLN = Vref + ISLPE x R9 VLN = Vref + ((Iline - ICC - 0.5 x 10-3 A)-Ip) x R9 System Logic Semiconductor SLS SL1062A Vref is an internally generated temperature compensated reference voltage of 3.7 V and R9 is an external resistor connected between SLPE and VEE. In normal use the value of R9 would be 20. Changing the value of R9 will also affect microphone gain, DTMF gain, gain control characteristics, sidetone level, maximum output swing on LN and the DC characteristics (especially at the lower voltages). Under normal conditions, when ISLPE>>ICC + 0.5 mA + Ip, the static behaviour of the circuit is that of a 3.7 V regulator diode with an internal resistance equal to that of R9. In the audio frequency range the dynamic impedance is largely determined by R1. Fig.2 shows the equivalent impedance of the circuit. The gain of the microphone amplifier can be adjusted between 44 dB and 52 dB to suit the sensitivity of the transducer in use. The gain is proportional to the value of R7 which is connected between GAS1 and GAS2. Stability is ensured by two external capacitors, C6 connected between GAS1 and SLPE and C8 connected between GAS1 and VEE. The value of C6 is 100 pF but this may be increased to obtain a firstorder low-pass filter. The value of C8 is 10 limes the value of C6. The cut-off frequency corresponds to the time constant R7 x C6. Input MUTE When MUTE is LOW or open circuit, the DTMF input is enabled and the microphone and receiving amplifier inputs are inhibited. The reverse is true when MUTE is HIGH, MUTE switching causes only negligible clicking on the line and earpiece output. If the number of parallel sets in use causes a drop in line current to below 6 mA the DTMF amplifier becomes active independent to the DC level applied to the MUTE input. Dial-tone multi-frequency input DTMF When the DTMF input is enabled dialling tones may be sent on to the line. The voltage gain from DTMF to LN is typically 25.5 dB (when R7 = 68 K) and varies with R7 in the same way as the microphone gain. The signalling tones can be heard in the earpiece at a low level (confidence tone). Receiving amplifier IR, QR and GAR The receiving amplifier has one input (IR) and a noninverting output (QR). The IR to QR gain is typically 31 dB (when R4 = 100 K). It can be adjusted between 20 and 31 dB to match the sensitivity of the transducer in use. The gain is set with the value of R4 which is connected between GAR and QR. The overall receive gain, between LN and QR, is calculated by subtracting the anti-sidetone network attenuation (32 dB) from the amplifier gain. Two external capacitors, C4 and C7, ensure stability. C4 is normally 100 pF and C7 is 10 times the value of C4. The value of C4 may be increased to obtain a firstorder low-pass filter. The cut-off frequency will depend on the time constant R4 x C4. The output voltage of the receiving amplifier is specified for continuous-wave drive. The maximum output voltage will be higher under speech conditions where the peak to RMS ratio is higher. Leq = C3 x R9 x RP RP = 16.2 K Figure 2. Equivalent impedance circuit At line currents below 9mA the internal reference voltage is automatically adjusted to a lower value (typically 1.6 V at 1 mA) This means that more sets can be operated in parallel with DC line voltages (excluding the polarity guard) down to an absolute minimum voltage of 1.6 V. At line currents below 9 mA the circuit has limited sending and receiving levels. The internal reference voltage can be adjusted by means of an external resistor (RVA). This resistor when connected between LN and REG will decrease the internal reference voltage and when connected between REG and SLPE will increase the internal reference voltage. Microphone inputs MIC+ and MIC- and gain pins GAS1 and GAS2 The circuit has symmetrical microphone inputs. Its input impedance is 64 K (2 x 32 K) and its voltage gain is typically 52 dB (when R7 = 68 K, see Figure 3). Dynamic, magnetic, piezo-electric or electret (with built-in FET source followers) can be used. SLS System Logic Semiconductor SL1062A Automatic gain control input AGC Automatic line loss compensation is achieved by connecting a resistor (R6) between AGC and VEE. The automatic gain control varies the gain of the microphone amplifier and the receiving amplifier in accordance with the DC line current. The control range is 5.8 dB which corresponds to a line length of 5 km for a 0.5 mm diameter twisted-pair copper cable with a DC resistance of 176 /km and average attenuation of 1.2 dB/km. Resistor R6 should be chosen in accordance with the exchange supply voltage and its feeding bridge resistance (see Table 1). Table 1 Values of resistor R6 for optimum line-loss compensation at various values of exchange supply voltage (Vexch) and exchange feeding bridge resistance (Rexch); R9 = 20 . Vexch(V) 36 48 60 400 Rexch() 100 140 600 800 Rexch() Rexch() R6(K) 78.7 110 93.1 120 1000 Rexch() 82 102 R9 and Zbal (see Fig4) suppresses the transmitted signal in the earpiece. Maximum compensation is obtained when the following conditions are fulfilled: R9 x R2 = R1 x Zbal = Zbal + R8 ( R3 + Zline Zline + R1 R8 x Zbal R8 +Zbal ) (1) (2) It fixed values are chosen for R1, R2, R3 and R9, then condition (1) will always be fulfilled when R8//Zbal< The ratio of start and stop currents of the AGS curve is independent of the value of R6. If no automatic line-loss compensation is required the AGS pin may be left open-circuit. The amplifiers, in this condition, will give their maximum specified gain. Sidetone suppression The anti-sidetone network, R1//Zline, R2, R3, R8, MAXIMUM RATINGS * Symbol VLN VLN(R) VLN(RM) Iline VIN Parameter Positive continuous line voltage Repetitive line voltage during switch-on or line interruption Repetitive peak line voltage for a 1 ms pulse per 5 s Line current Input voltage on all other pins R9 = 20 ; R10 = 13 ; see Fig.5 R9 = 20 positive input voltage negative input voltage PD Tstg * Condition Min -40 Max 12 13.2 28 140 VCC+0.7 -0.7 666 +125 Unit V V V mA V V mW C Total power dissipation Storage temperature R9 = 20 ; note 1 Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Note 1. Calculated for the maximum operating temperature specified (Tamb = 75C) and a maximum junction temperature of 125C. System Logic Semiconductor SLS SL1062A RECOMMENDED OPERATING CONDITIONS Symbol Iline Parameter Operating line current normal operation with reduced performance Supply voltage for peripherals Voltage gain microphone amplifier receiving amplifier Operating ambient temperature Iline = 15 mA Ip = 1.2 mA; MUTE = LOW Ip = 0 mA; MUTE = LOW Conditions Min 11 1 2.2 44 20 -25 Typ 3.4 Max 140 11 52 31 +75 Unit mA mA V V dB dB C VCC GV Tamb Line loss compensation GV Vexch Rexch Gain control Exchange supply voltage Exchange feeding bridge resistance 36 0.4 5.8 60 1 dB V K This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ). CC Unused outputs must be left open. ELECTRICAL CHARACTERISTICS(Iline = 11 to 140 mA; VEE = 0 V; f = 800 Hz;Tamb = 25C; unless other specified) Symbol Parameter Test Conditions Guaranteed Limits Min Supplies LN and VCC (pins 1 and 13) VLN Voltage Drop Over Circuit between LN and VEE MIC Inputs Open-Circuit Iline = 1 mA Iline = 4 mA Iline = 15 mA Iline = 100 mA Iline = 140 mA Iline = 15 mA Iline = 15 mA RVA (LN to REG)=68K RVA (LN to SLPE)=39K VCC = 2.8 V V 3.56 4.9 1.6 1.9 -0.3 3.5 4.5 1.35 mA (continued) 4.25 6.5 7.5 mV/K V Typ Max Unit VLN/T VLN Variation with Temperature Voltage Drop Over Circuit between LN and VEE with External Resistor RVA Supply Current ICC SLS System Logic Semiconductor SL1062A ELECTRICAL CHARACTERISTICS(Iline = 11 to 140 mA; VEE = 0 V; f = 800 Hz;Tamb = 25C; unless other specified) Symbol Parameter Test Conditions Guaranteed Limits Min Microphone inputs MIC- and MIC+ (pins 6 and 7) Zi Input Impedance differential single-ended Common Mode Rejection Ratio Voltage Gain MIC+ or MICto LN Gain Variation with Frequency Reference to 800 Hz Gain Variation with Temperature Referenced to 25C Input Impedance Voltage Gain from DTMF to LN Gain Variation with Frequency Reference to 800 Hz Gain Variation with Temperature Referenced to 25C Iline 15 mA; R7 = 68 K f = 300 and 3400 Hz Iline = 15 mA R7 = 68 K f = 300 and 3400 Hz K between MIC- and MIC+ MIC- or MIC+ to VEE 50.5 0.2 64 32 82 53.5 dB dB dB Typ Max Unit CMRR Gv Gvf GvT without R6; Iline =50 mA; Tamb = -25 and +75C - 0.2 - dB DTMF input (pin 11) Zi Gv Gvf 24.0 20.7 0.2 27.0 K dB dB GvT Iline =50 mA; Tamb = -25 and +75C - 0.2 - dB Gain Adjustment Inputs GAS1 and GAS2 (pins 2 and 3) Gv Transmitting Amplifier Gain Variation by Adjustment of R7 between GAS1 and GAS2 Output Voltage (RMS value) THD = 10% Iline = 4 mA Iline = 15 mA Iline = 15 mA; R7 =68K 200 between MIC- and MIC+ -8 0 dB Sending Amplifier Output LN (pin 1) VLN(rms) V 1.7 0.8 -69 dBmp Vno(rms) Noise Output Voltage (RMS value) Receiving Amplifier Input IR (pin 10) Zi Zo Gv Input Impedance Output Impedance Voltage Gain from IR to QR Iline 15 mA; RL = 300 (from pin 9 to pin 4) 29.5 21 4 32.5 K dB (continued) Receiving amplifier output QR (pin 4) SLS System Logic Semiconductor SL1062A ELECTRICAL CHARACTERISTICS(Iline = 11 to 140 mA; VEE = 0 V; f = 800 Hz;Tamb = 25C; unless other specified) Symbol Gvf Parameter Test Conditions Guaranteed Limits Min Gain Variation with Frequency Reference to 800 Hz Gain Variation with Temperature Referenced to 25C Output Voltage (RMS value) f = 300 and 3400 Hz Typ 0.2 Max dB Unit GvT without R6; Iline =50 mA; Tamb = -25 and +75C THD = 2%; sine wave drive: R4 = 100 K; Iline = 15 mA; Ip = 0 mA RL = 150 RL = 450 THD=10%; R4=100 K; Iline = 4 mA; RL = 150 Iline = 15 mA; R4=100K IR open-circuit psophometrically weighted; RL =300 - 0.2 - dB Vo(rms) V 0.22 0.3 - 15 50 mV V Vo(rms) Vno(rms) Output Voltage (RMS value) Noise Output Voltage (RMS value) Gain Adjustment Input GAR (pin 5) Gv Receiving Amplifier Gain Variation by Adjustment of R4 between GAR and OR -11 0 dB Mute Input (pin 12) VIH VIL IMUTE Gv Gv HIGH Level Input Voltage LOW Level Input Voltage Input Current 1.5 VCC 0.3 15 V V A Raduction of Gain MIC+ or MIC- to LN Voltage Gain from DTMF to QR MUTE = LOW R4 = 100 K RL = 300 70 -17 dB dB Automatic Gain Control Input AGC (pin 15) Gv Controlling the Gain from IR to QR and the Gain from MIC+, MIC- to LN Gain Control Range Highest Line Current for Maximum Gain Lowest Line Current for Minimum Gain R6 = 110 K (between AGC and VEE) Iline = 70 mA -5.8 23 61 dB mA mA IlineH IlineL SLS System Logic Semiconductor SL1062A Voltage gain is defined as GV = 20 log VO VI For measuring gain from MIC+ and MIC- the MUTE input should be HIGH. For measuring the DTMF input, the MUTE input should be LOW or open-circuit. Inputs not being tested should be open-circuit. Figure 3. Test circuit for defining SL1062A voltage gain of MIC+, MIC- and DTMF inputs. Figure 4. Equivalent circuit of SL1062A anti-sidetone bridge SLS System Logic Semiconductor SL1062A The diode bridge, the Zener diode and R10 limit the current into, and the voltage across, the circuit during line transients. A different protaction arrangement is required for pulse dialling or register recall. The DC line voltage can be set to a higher value by the resistor RVA (REG to SLPE). Figure 5. Typical application of SL1062A, with piezo-electric earpiece and DTMF dialling. SLS System Logic Semiconductor |
Price & Availability of SL1062A
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |